Generally in computer systems and especially in personal computer systems, data is transferred between various system devices such as a central processing unit (CPU), memory devices, and direct memory access (DMA) controllers. In addition, data is transferred between expansion elements such as input/output (I/O) devices, and between these I/O devices and the various system devices. The I/O devices and the system devices communicate with and amongst each other over computer buses, which comprise a series of conductors along which information is transmitted from any of several sources to any of several destinations. Many of the system devices and the I/O devices are capable of serving as bus controllers (i.e., devices which can control the computer system) and bus slaves (i.e., elements which are controlled by bus controllers).
Personal computer systems having more than one bus are known. Typically, a local bus is provided over which the CPU communicates with cache memory or a memory controller, and a system I/O bus is provided over which system bus devices such as the DMA controller, or the I/O devices, communicate with the system memory via the memory controller. The system I/O bus comprises a system bus and an I/O bus connected by a bus interface unit. The I/O devices communicate with one another over the I/O bus. The I/O devices are also typically required to communicate with system bus devices such as system memory. Such communications must travel over both the I/O bus and the system bus through the bus interface unit.
In the case of reading and writing data between different buses, and particularly in the case when an I/O bus master device is writing data to or reading data from system memory, parity errors can occur. It is essential that these errors be identified to the CPU or other device so that appropriate action can be taken.
Accordingly, it is an object of this invention to provide a parity error recovery system which will detect and flag parity errors occurring during a read from or write to system memory by a device coupled to the I/O bus which is acting as a bus master in control of the I/O bus. Also, to capture the address at which the error occurred and to make it available to the system for appropriate action.